TMCnews Featured Article
September 25, 2008
OKI Network LSI Leverages Cadence OVM
By Jayashree Adkoli, TMCnet Contributor
San Jose, Calif.-based Cadence Design Systems announced that OKI (News - Alert) Network LSI is reaping benefits by utilizing the company’s open verification methodology (OVM) and Incisive functional verification technology.
"OKI Network LSI is one of many companies recognizing the benefits of the Open Verification Methodology," said Michal Siwinski, marketing director of enterprise verification group at Cadence. "The company has discovered that transitioning to the OVM can be a very smooth process that pays dividends quickly."
The OVM, which was released last year, has been jointly developed by Cadence and Mentor Graphics (News - Alert) to enable true SystemVerilog interoperability with a standard library and a proven methodology. It is an open-source, multi-vendor SystemVerilog class library and verification methodology, which defines a framework for reusable verification IP (VIP) and tests.
SystemVerilog is an evolving solution and candidate IEEE (News - Alert) P1800 standard that expands on base Verilog language. SystemVerilog can add convenience and abstraction extensions for design.
Cadence Incisive functional verification platform mainly enables manufactures to have productivity gains in the verification of complex, multi-million-gate system-on-chip (SoC) designs. The verification technology can compress overall verification time by as much as 50 percent, the company says.
OKI Network LSI provides third-party verification services for huge system on chips (SoCs), which enables advanced on-chip buses such as AXI and OCP (News - Alert). According to the company, an advanced verification technology such as the OVM is required to build huge SoCs.
Key benefits that OKI Network LSI reported by leveraging Cadence OVM and Incisive methodology include: ability to utilize sequences for controlling test scenarios and testbench development; optimizing the test scenarios for simulation that reduced regression test time by 90 percent, which was achieved by combining Incisive coverage-ranking capability with the OVM; and ability to build highly-reusable testbench that would provide overall project time savings of about 50 percent by utilizing Cadence Incisive functional verification platform.
"Our clients need a verification solution that can scale for sophisticated System on Chip (SoC) applications," said Takahiro Kobori, senior general manager, LSI design and development division. "The scalable, open, interoperable nature of the OVM makes it ideal for our clients and we found the transition to it has been quite smooth. In particular, the configuration was easy, and the built-in architecture for verification components enabled us to quickly create highly-reusable verification IP."
Cadence enables creation of integrated circuits and electronics, where its customers utilize the company’s software and hardware, methodologies, and services – to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment and computer systems.
Jayashree Adkoli is a contributing editor for TMCnet. To read more of Jayashree's articles, please visit her columnist page.
Edited by Eve Sullivan