TMCnews Featured Article
April 14, 2009
Cavium Networks Intros OCTEON II IAP Family of Multi-Core MIPS64 Processors
By Anshu Shrivastava, TMCnet Contributor
Cavium Networks has introduced OCTEON II Internet Application Processor (News - Alert) (IAP) family of multi-core MIPS64 processors.
The OCTEON II IAP offers up to 4x performance over the existing OCTEON Plus processor family, and features more than twice the performance/watt, according to company officials.
The new OCTEON II IAP processor family is designed to fuel the voice, video and data convergence driven by cloud computing, virtualization, high definition (HD) video over IP, Web 2.0 and mobile 3G/4G applications.
Company officials say the OCTEON Multi-core MIPS64 processors have been a driving force for multi-core adoption at major Tier-1 networking, wireless, and storage OEMs worldwide.
Cavium has simplified multi-core development by providing support for standard operating systems, GNU tool-chains, C/C++ based software applications and hardware acceleration engines with an advanced multi-core scheduler.
The OCTEON II IAP family integrates 1 to 32 custom cnMIPS64 cores, up to 75 Application Acceleration Engines for QoS, packet processing, TCP, compression, encryption, RAID, de-duplication and regular expression.
In addition, officials say it integrates a set of networking I/Os including gigabit Ethernet, 10 gigabit Ethernet, PCI Express Gen 2, USB2.0, serial Rapid I/O (sRIO) and Interlaken.
Also, OCTEON II features a new Hyperconnect crossbar with low-latency and virtualization features, up to 400Gbps of DDR3 memory bandwidth, up to 100Gbps of network connectivity.
The OCTEON II family uses the on-chip Power Optimizer, and it consumes only 2W to 60W across the entire family. Officials say the OCTEON II Software Development Kit (SDK) builds upon the existing OCTEON SDK.
And, officials say it includes Linux SMP, GNU Toolchain, Simple Executive for fast path applications, performance tools, simulator, feature rich APIs for hardware acceleration and more.
“Cavium's OCTEON II family sets a new standard in performance and integration. Working closely together, we are providing the software foundation for customer applications to easily harness the full power of OCTEON II's 32 cores,” said Ken Klein, president and CEO at Wind River, in a release.
Syed Ali, president and CEO at Cavium Networks (News - Alert), believes that the OCTEON II will fuel the growth of emerging hyper-network applications such as cloud computing, data center virtualization, smart storage, 4G/LTE (News - Alert) wireless, HD video over the Internet and multimedia rich Web 2.0 applications.
The OCTEON II CN63XX is an integrated SOC with 2 to 6 MIPS64 cores. It is targeted for mainstream high-volume applications such as enterprise routers, switches, appliances, 3G/4G base stations and intelligent storage and server adapters.
The OCTEON II family includes four different product lines: the CN68XX (16 to 32 cores), CN66XX (8 to 16 cores), CN63XX (2 to 6 cores) and CN62XX (1 to 4 cores).
Officials said that the first OCTEON II product line that will be commercially available will be the CN63XX which will be followed by the CN68XX.
The OCTEON II IAP offers up to 4x performance over the existing OCTEON Plus processor family, and features more than twice the performance/watt, according to company officials.
The new OCTEON II IAP processor family is designed to fuel the voice, video and data convergence driven by cloud computing, virtualization, high definition (HD) video over IP, Web 2.0 and mobile 3G/4G applications.
Company officials say the OCTEON Multi-core MIPS64 processors have been a driving force for multi-core adoption at major Tier-1 networking, wireless, and storage OEMs worldwide.
Cavium has simplified multi-core development by providing support for standard operating systems, GNU tool-chains, C/C++ based software applications and hardware acceleration engines with an advanced multi-core scheduler.
The OCTEON II IAP family integrates 1 to 32 custom cnMIPS64 cores, up to 75 Application Acceleration Engines for QoS, packet processing, TCP, compression, encryption, RAID, de-duplication and regular expression.
In addition, officials say it integrates a set of networking I/Os including gigabit Ethernet, 10 gigabit Ethernet, PCI Express Gen 2, USB2.0, serial Rapid I/O (sRIO) and Interlaken.
Also, OCTEON II features a new Hyperconnect crossbar with low-latency and virtualization features, up to 400Gbps of DDR3 memory bandwidth, up to 100Gbps of network connectivity.
The OCTEON II family uses the on-chip Power Optimizer, and it consumes only 2W to 60W across the entire family. Officials say the OCTEON II Software Development Kit (SDK) builds upon the existing OCTEON SDK.
And, officials say it includes Linux SMP, GNU Toolchain, Simple Executive for fast path applications, performance tools, simulator, feature rich APIs for hardware acceleration and more.
“Cavium's OCTEON II family sets a new standard in performance and integration. Working closely together, we are providing the software foundation for customer applications to easily harness the full power of OCTEON II's 32 cores,” said Ken Klein, president and CEO at Wind River, in a release.
Syed Ali, president and CEO at Cavium Networks (News - Alert), believes that the OCTEON II will fuel the growth of emerging hyper-network applications such as cloud computing, data center virtualization, smart storage, 4G/LTE (News - Alert) wireless, HD video over the Internet and multimedia rich Web 2.0 applications.
The OCTEON II CN63XX is an integrated SOC with 2 to 6 MIPS64 cores. It is targeted for mainstream high-volume applications such as enterprise routers, switches, appliances, 3G/4G base stations and intelligent storage and server adapters.
The OCTEON II family includes four different product lines: the CN68XX (16 to 32 cores), CN66XX (8 to 16 cores), CN63XX (2 to 6 cores) and CN62XX (1 to 4 cores).
Officials said that the first OCTEON II product line that will be commercially available will be the CN63XX which will be followed by the CN68XX.
Anshu Shrivastava is a contributing editor for TMCnet. To read more of Anshu’s articles, please visit her columnist page.
Edited by Patrick Barnard
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