TMCnews Featured Article
July 15, 2009
Satin IP and STMicroelectronics Deliver Design Quality Closure
By Vivek Naik, TMCnet Contributor
Satin IP Technologies has announced that it collaborated with the Home Entertainment and Display or, “HED” product group of STMicroelectronics and has successfully built-in and delivered Quality closure.
Officials at the company claimed the joint objective of monitoring and improving the quality of STMicroelectronics’ (News - Alert) internally developed semiconductor Intellectual Property blocks was successfully achieved as per this partnership. Although ST has evolved comprehensive and clear design standards that have been ratified for quality over the years, these became inadequate in computational terms once the current number of more than 50 Intellectual Property blocks for the SoCs increased the complexity of architecture and exponentially pumped up the data to be monitored.
To bridge all the resulting gaps, said official, ST’s HED group first sat down with Satin IP’s quality team to clearly define all requirements, and then the two companies worked out an accurate and workable method that essentially revolves around Satin IP’s VIP Lane solution, which extracts key data from the Intellectual Property design flow, achieves on the fly quality monitoring during the development cycle, provides automated production of Intellectual Property integration documents, and delivers more controlled supervision of all the Intellectual Property blocks of a defined SoC.
“VIP Lane adds new capabilities to the quality design flow that HED has been working on for years,” said François Rémond, computer aided design and design methodology director at the HED Product Group for ST. “These enlarged capabilities lead to faster identification of quality metrics requiring special attention, better communication between IP and SoC design teams and measured savings on design time to integration.”
“ST has a long history of defining design practices and deploying tools for developing IP blocks that integrate smoothly,” also said Michel Tabusse, Chief Executive Officer of Satin IP Technologies. “These practices and tools led to the definition of quality metrics that VIP Lane was able to automate to help ST with monitoring and deployment. And ST can maintain these metrics in the long term.”
Officials at the company claimed the joint objective of monitoring and improving the quality of STMicroelectronics’ (News - Alert) internally developed semiconductor Intellectual Property blocks was successfully achieved as per this partnership. Although ST has evolved comprehensive and clear design standards that have been ratified for quality over the years, these became inadequate in computational terms once the current number of more than 50 Intellectual Property blocks for the SoCs increased the complexity of architecture and exponentially pumped up the data to be monitored.
To bridge all the resulting gaps, said official, ST’s HED group first sat down with Satin IP’s quality team to clearly define all requirements, and then the two companies worked out an accurate and workable method that essentially revolves around Satin IP’s VIP Lane solution, which extracts key data from the Intellectual Property design flow, achieves on the fly quality monitoring during the development cycle, provides automated production of Intellectual Property integration documents, and delivers more controlled supervision of all the Intellectual Property blocks of a defined SoC.
“VIP Lane adds new capabilities to the quality design flow that HED has been working on for years,” said François Rémond, computer aided design and design methodology director at the HED Product Group for ST. “These enlarged capabilities lead to faster identification of quality metrics requiring special attention, better communication between IP and SoC design teams and measured savings on design time to integration.”
“ST has a long history of defining design practices and deploying tools for developing IP blocks that integrate smoothly,” also said Michel Tabusse, Chief Executive Officer of Satin IP Technologies. “These practices and tools led to the definition of quality metrics that VIP Lane was able to automate to help ST with monitoring and deployment. And ST can maintain these metrics in the long term.”
Vivek Naik is a contributing editor for TMCnet. To read more of Vivek's articles, please visit his columnist page.
Edited by Stefania Viscusi
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